1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a technique for thinning a semiconductor wafer.
2. Description of the Background Art
In the field of memory, microprocessor, or the like, dense packaging using three dimensional packaging or the like has been developed in semiconductor devices. With the development of dense packaging, it is required to reduce the thickness of a semiconductor wafer, and today, the thickness of a semiconductor wafer at the time of completion of a process for manufacturing a semiconductor device is reduced to about 25 μm.
Further, in inverter circuits such as industrial motors, automobile motors, and the like, power supply devices for mass-storage servers, uninterruptible power supplies, and the like, power semiconductor devices for handling relatively large power mainly ranging from several hundreds kilowatts to several megawatts are sometimes used. Such power semiconductor devices each include a semiconductor switch such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), or the like. As IGBTs, conventionally, planar gate type ones have been widely used, but recently, vertical IGBTs using trench gates are used for high integration.
In such power semiconductor devices, a thinning process for thinning semiconductor wafers is performed in order to improve energization performance such as On-state characteristics. In recent years, devices are manufactured through an ultra-thin wafer process thinning wafers which are manufactured by wafer materials obtained by the FZ (Floating Zone) method, up to about 60 μm, for improvement in terms of cost and characteristics.
In the process for thinning semiconductor wafers, generally, mechanical grinding (polishing) such as backgrinding or polishing and chemical grinding (polishing) such as wet etching, dry etching, or the like for removing processing distortion caused by the mechanical grinding are performed, and then various processings are performed. In order to prevent the breakage of the semiconductor wafer due to the uneven structure formed thereon or the like in the grinding process, conventionally, a surface protection tape is attached as a reinforcing member and a step absorbing member onto a surface of the semiconductor wafer on which the uneven structure is formed.
In a case of thin devices used in recent year, however, since the proportion of the unevenness to the total thickness of the device increases, the absorption of the unevenness by the surface protection tape is insufficient and the semiconductor wafer is sometimes broken in the grinding process.
In order to solve the above problem, Japanese Patent Application Laid Open Gazette No. 2005-317570 (Patent Document 1) proposes a method in which the semiconductor wafer is heated after the surface protection tape is attached onto a surface thereof, whereby the surface protection tape is deformed to ease the level differences formed on the surface of the semiconductor wafer, and this prevents the breakage of the semiconductor wafer in the process for manufacturing a semiconductor element. Further, Japanese Patent Application Laid Open Gazette No. 2006-196710 (Patent Document 2) proposes a method in which a surface protection tape comprising an adhesive layer having a thickness larger than the height of the unevenness is used, to thereby ease high level differences formed on the surface of the surface protection tape.
The methods in which the surface protection tape is attached onto the surface of the semiconductor wafer, however, can produce an insufficient effect of suppressing the effect of the unevenness, and consequently, there remain some cases where the wafer is broken. There arises another problem that a large number of foreign matters remain on the surface of the semiconductor wafer after a series of process steps executed on the semiconductor wafer are completed.